A Power and Area Eﬃcient CMOS Bandgap Reference Circuit with an Integrated Voltage-Reference Branch

This work presents a compact and low power bandgap voltage reference design using self-biased current mirror circuit. This design eliminates the standard complementary-to-absolute-temperature (CTAT) bipolar device in the voltage-reference branch, reducing the bipolar area by 20 percent. Instead, the design shares the same bipolar device in the main CTAT branch for generating the reference voltage. An additional beneﬁt of eliminating the voltage-reference branch is the reduction of total power consumption by approximately 30 percent. This novel topology reduces power and area of the core bandgap reference circuit without compromising temperature drift performance. Designed, fabricated and functionally tested in a 0 . 6 µm CMOS process. The simulation result shows the temperature coeﬃcient of this design is 6 . 3 ppm/ ◦ C for a temperature range of − 40 ◦ C to 125 ◦ C . This bandgap reference design occupies a silicon area of 0 . 018 mm 2 and draws an average quiescent current of 2 µA from a supply voltage of 3 . 3 − 5 V . The simulated ﬂicker voltage noise is 4 . 34 µV/ √ Hz at 10 Hz .


Introduction
Voltage reference circuits are an essential block in most applications from a simple integrated circuit (IC) to a large System-on-Chip (SoC) ranging from purely digital circuits to mixed-signal applications such as Analog to Digital converters (ADCs), Digital to Analog converters (DACs), phase locked loops (PLLs), low noise amplifiers (LNAs), digital multimeters, battery chargers, low-power IoT sensor nodes, portable data acquisition systems and so on.Since the first bandgap reference (BGR) circuit introduced by Robert Widlar Widlar ( ), BGR has been widely used since it provides a well-defined voltage reference with a very weak dependence on process, voltage and temperature.Most analog and mixed-signal circuits also require a current reference that sets the internal bias current for the circuits.The BGR can also provide a reference current directly which has positive temperature co-efficient (PTC).For most bias currents, a PTC reference current is sufficient.For circuits demanding more stable current reference can achieve so with some additional circuits Ji et al. ( ).
Figure , shows two type of traditional BGR circuit: (a) one using operational amplifier (Op-Amp) and (b) using self-biased current mirror circuit Wu et al. ( ).The principle of operations is the same in both cases where the nodes A and B are forced to be the same by (a) the Op-Amp or (b) the self-biased current mirror.Forcing same node voltages makes the voltage drop across R 1 be exactly difference between the base-to-emitter voltage V BE of the two bi-polar transistor provided that, the size of the transistor Q 1 = N •Q 2 .The voltage across the resistor R 1 produces a proportional-to-absolute-temperature (PTAT) voltage, which is multiplied with a suitable constant and added to V BE of Q 3 to generate a stable voltage Allen and Holberg ( ) as follows: Where, V REF is the output reference voltage and V T is the thermal voltage of the semiconductor.
Typically, Op-Amp based BGR is preferred over self-biased for better power supply rejection (PSR) performance and lower supply requirement.Although the self-biased BGR may have a lower performance in those two metrics, it is a simpler design consuming less area and power while achieving almost similar ).In this paper an improved self-biased based bandgap reference circuit has been proposed which further lowers the area and power of the reference circuit while preserving the temperature coefficient performance.The improved circuit generates the reference voltage without using the separate reference-voltage branch as in the traditional self-biased BGR.This paper is organized as follows: Section II describes the proposed architecture of the BGR along with its design procedure and circuit implementation.Simulation and measurement results are presented in Section III, followed by a conclusion in Section IV.

Proposed bandgap reference
Figure shows the core part of the proposed bandgap reference circuit.As evident from the figure, this modified circuit avoids a bi-polar device in the reference branch.Here the BJT Q 2 used for dual purpose; firstly, it helps for generating a PTAT voltage across resistor R 1 and secondly, voltage across this adds with voltage across R 2 for generating reference voltage V REF at the output node.This elegant modification in the traditional self-biased current mirror based BGR provides some great advantages particularly in power consumption and silicon area of the core circuit.These advantages are; • Since we eliminate the standard voltage-reference branch, the bi-polar device area reduces by approximately percent and the PMOS current-mirror area reduces by approximately percent.Note that, bi-polar devices and the current mirrors are a significant portion of the core BGR area., • One-third of the total current is reduced in the core BGR and therefore one-third reduction in power consumption in the core BGR circuit as well.
The self-biased current mirror uses two P-MOS transistor M P 1 , M P 2 and two N-MOS transistor M N 1 , M N 2 .These four transistor forms the self-biased feedback loop which makes the node voltages at A and B equal.The second branch of the circuit uses a single bi-polar device Q 2 , which produces a CTAT voltage V BE2 across the BJT Q 2 , whereas, in the first branch, four parallel BJTs are connected with a resistor R 1 in series.As both the node voltages at A and B are same and current flowing through both the BJTs are As V BE2 is a CTAT voltage and dV BE is a PTAT voltage, so addition of CTAT voltage with some appropriate constant multiplication of the PTAT voltage will generate a reference voltage which will be zero temperature coefficients at a reference temperature.
The power-supply rejection (PSR) performance does not change significantly from the traditional selfbiased BGR.The PSR can be improved by using cascode current mirrors Wu et al. ( ) or symmetric biasing of both the branches Lam and Ki ( ).Our proposed integration of reference branch will also work with symmetric biasing as shown in Lam and Ki ( ).

. Design Procedure of improved BGR
In this section, the expressions to calculate the resistance values of the core BGR circuit for a current value will be shown.For a low power BGR, Q 1 and Q 2 were each biased with 1µA.Given the bias current, R 1 can be expressed as: Where V T is the thermal voltage of the semiconductor and its value at room temperature is approximately 25.8 mV .Applying the values of V T and I 1 in Equation , R 1 evaluates to 35.76 kΩ.
The reference voltage can be calculated by combining the voltage across the BJT Q 2 (CTAT in nature) and voltage across the resistor R 2 (PTAT in nature) as; Where, V R2 is the PTAT voltage across resistor R 2 and can be expressed as: Equation can be rewritten as; For calculating zero temperature coefficient reference voltage at the reference temperature, the derivative of V REF should be zero.
Using ∂V BE2 /∂T = −1.6mV/ • C and ∂V T /∂T = 85 µV / • C Allen and Holberg ( ) in Equation , α evaluates to 18.82 and using Equation , V REF evaluats to 1.155 V For this modified architecture the current flowing through resistor R 2 is half of that current flowing in resistor R 1 .So the constant α for this circuit will be; Applying α and R 1 values in Equation , R 2 evaluates to 971 kΩ. .), to ensure the minimum systematic offset in I 1 and I 2 .As mentioned before, this systematic offset can be minimized by using cascode current mirrors Wu et al. ( ) or symmetric biasing of both the branches Lam and Ki (

Implementation of complete BGR
).The unit sizes of Q 1 and Q 2 are chosen to be the minimum allowable in the implemented technology and the ratio between them is chosen such that the area of Q 1−2 and R 1−2 is minimized.For the implemented technology, the BJT ratio 4 : 1 was found to be optimum.
A high-sheet-rho poly resistor (R sheet = 3.76 kΩ/sq) was chosen to minimize the resistor area.In order to trim the output temperature coefficient (TC) of the BGR after fabrication, R 2 is a -bit programmable resistor is used as shown in Figure , which is programmed through an Inter-IC Communication (I C) protocol with a range of 890 − 940 kΩ.Each of the programmable resistor in R 2 is made of series-parallel combination of unit resistors of 20 kΩ.R 1 is also constructed from combination of same unit resistors so they can be matched in layout with R 2 .During startup, M P S 2 ensures that the current mirror is pulled out of the zero-V gs state and once the circuit is operating normally (V REF ≈ 1.155), the voltage drop across M N S 1 should be high enough that it shuts OFF M P S 2 .M N S 1 needs to be sized such that there is no leakage current during normal operation.M P S 1 provides a trickle current for M N S 1 and M N S 1 is sized with a very long length transistor to provide a large voltage drop for the minimum amount of current.For layout, special care is taken to match M P 1−3 , M N 1−2 , R 1−2 , and Q 1−2 which affects the TC directly.

. Simulation results
The improved self-biased bandgap reference has been simulated with a commercially available Spectre simulator using the Process Design Kit (PDK) from the foundry.The first order temperature drift performance is simulated over the entire temperature range of −40  .

Test setup and measurement results
This work has been fabricated in a commercially available 0.6 µm CMOS technology.The proposed work has been integrated to provide bias voltage to other blocks inside the chip.At the time of this writing, ability to do a full temperature characterization using an environmental chamber along with R 2 trimming through I 2 C was unavailable.A functional test of the fabricated BGR was done using the test setup as shown in Figure with the R 2 set to the default value.For the functional test, the packaged silicon chip is mounted on a temporary prototype board to test the functionality.We used a buffer (OP-) at the output of chip to avoid loading from the low-impedance measurement device.A hot air stream was used to heat the device to temperatures between 25 • C to 100 • C from the top side of the chip.The temperature was changed by changing the distance between the source of the hot air stream and the device.The output of the BGR was measured using high precision ( -/ digit) voltage meter (Keysight A).After each temperature value settled, the temperature of the device was measured using a mounted laser-guided infrared thermometer.The device was powered using a programmable power supply (Keysight E A) Figure shows the measurement result of output voltage versus temperature.As seen from the result, the untrimmed temperature coefficient is strongly PTAT in nature (115 ppm/ • C).Some of the random mismatch pairs that could contribute to this are M P 2−3 , R 1 and R 2 ratio, Q 1−2 and M N 1−2 as well.In simulation, when R 2 is increased by .percentage and V T offset value of σV T / √ A is applied between M P 2−3 and M N 1−2 the simulation results match the test result as shown in Figure For the same offsets added as for the tempco simulation, the line regulation in both simulations and measurements match closely showing a line regulation of 16mV /V as shown in Figure .On availability of an environment chamber, we will be able to get to the root of the tempco response by doing accurate temperature characterization for different R 2 trim values.

Conclusion
In this paper, a self-biased based BGR was improved for area and power by eliminating the referencevoltage branch and integrating it in the main core without compromising temperature drift performance.By using the CTAT voltage in the core of the BGR to generate the reference voltage (V REF ), the power consumption of the core and area of the BJTs reduces by percent and percent respectively.The BGR is implemented in a .-µ m CMOS process with an area of 0.018 mm 2 that includes the core bandgap and bias currents.This architecture greatly simplifies the design complexity with a temperature coefficient of 6.3 ppm/ • C for a temperature range of −40 • C to 125 • C from simulation.The simulated PSR is dB at kHz which can be improved by using the cascode self-biased current mirror.This architecture gives a spot noise of 4.34µV / √ Hz dominated by the flicker noise of NMOS and PMOS current-mirrors.The flicker noise can be reduced by increasing the area of those devices or chopping the current mirror.

Figure :
Figure : Core part of the proposed self-biased current mirror based BGR

Figure :
Figure : Complete schematic diagram of the proposed BGR circuit

Figure
Figure shows the complete implementation of the proposed BGR.M P 1−3 , M N 1−2 , R 1−2 , and Q 1−2 forms the core part of the bandgap and the value of the resistors are calculated in the previous sub-section.M P S 1−2 and M N S 1 form the start up circuitry since there are two stable states.M P B transistors are the PTAT current sources for biasing internal circuits.M N 1−2 are biased in the deep-sub-threshold (weak inversion) region to provide the maximum g m /I D for given bias current Harrison and Charles ( ), which ensures the voltages of node A and B are only offset by the V T mismatch of the M N 1−2 and the systematic offset of I 1 and I 2 .Typically, g m /I D > 20 ensures deep-sub-threshold operation.Please note that, this offset is similar to a offset in a Op-Amp based BGR where the input referred offset of the Op-Amp is dominated by the V T mismatch of the input pair of the differential amplifier which also biased in deep-subthreshold region for low-power application.PMOS current mirrors M P 1−3 and M P B are biased in saturation region where g m /I D is typically less than Harrison and Charles (), to ensure the minimum systematic offset in I 1 and I 2 .As mentioned before, this systematic offset can be minimized by using cascode current mirrorsWu et al. (   ) or symmetric biasing of both the branches Lam and Ki ().The unit sizes of Q 1 and Q 2 are chosen to be the minimum allowable in the implemented technology and the ratio between them is chosen such that the area of Q 1−2 and R 1−2 is minimized.For the implemented technology, the BJT ratio 4 : 1 was found to be optimum.

Figure :
Figure : Simulation result: VREF versus Temperature for different R 2 trims.
The calculated temperature coefficient (TC) from figure is 6.3 ppm/ • C. Figure , shows the parametric plot of VREF versus temperature at all ( -bit) trimming resistance values.The simulated PSR performance at room temperature for the improved BGR circuit is about dB at DC and dB at kHz.The noise performance at room temperature is 4.34 µV / √ Hz at Hz and 1.47 µV / √ Hz at Hz which is dominated by the flicker noise of current-mirrors, M N 1−2 ( percentage) and M P 1−3 ( percentage).The simulated average quiescent current is about 2 µA over the temperature range of −40 • C to 125 • C.
Figure shows the chip micrograph with highlighting the proposed BGR and its corresponding layout view.The whole BGR consumes 0.018 mm 2 of silicon area inside the chip.

Figure :
Figure : Chip micrograph and Layout of proposed BGR.

Figure :
Figure : Test Setup for the functional verification of the fabricated BGR.

Figure :
Figure : Line Regulation: Measurement and Simulation.

Table :
Summary of the Simulation Results.
Table summarizes the simulation parameters in and its corresponding simulated values.