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@book{patterson2020computer,
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@article{zaruba2019ariane,
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@misc{serv2019,
  title        = {{SERV}: The {SErial} {RISC-V} {CPU}},
  author       = {Kindgren, Olof},
  year         = {2019},
  howpublished = {\url{https://github.com/olofk/serv}},
  note         = {Accessed May 2026}
}

@misc{picorv32,
  title        = {{PicoRV32}: A Size-Optimized {RISC-V} {CPU}},
  author       = {Wolf, Clifford},
  year         = {2017},
  howpublished = {\url{https://github.com/YosysHQ/picorv32}},
  note         = {Accessed May 2026}
}

@misc{vexriscv,
  title        = {{VexRiscv}: A {RISC-V} implementation written in {SpinalHDL}},
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  year         = {2018},
  howpublished = {\url{https://github.com/SpinalHDL/VexRiscv}},
  note         = {Accessed May 2026}
}

@misc{swerv2019,
  title        = {{SweRV} {EH1} {RISC-V} Core},
  author       = {{Western Digital Corporation}},
  year         = {2019},
  howpublished = {\url{https://github.com/chipsalliance/Cores-SweRV}},
  note         = {Accessed May 2026}
}

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  year        = {2016}
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