Comments on "Dual-rail asynchronous logic multi-level implementation"

P Balasubramanian

doi:10.31224/osf.io/3aynr

Preprint has been published in a journal as an article
DOI of the published article https://doi.org/10.1016/j.vlsi.2015.08.001

Preprint / Version 1

Comments on "Dual-rail asynchronous logic multi-level implementation"

##article.authors##

P Balasubramanian https://orcid.org/0000-0001-9412-4773

DOI:

https://doi.org/10.31224/osf.io/3aynr

Keywords:

Asynchronous logic, Boolean network, Decomposition, Multi-level implementation, Node

Abstract

In this research communication, we comment on “Dual-rail asynchronous logic multi-level implementation” [Integration, the VLSI Journal 47 (2014) 148–159] by expounding the problematic issues, and provide some clarifications on delay-insensitivity, robust asynchronous logic, multi-level decomposition, and physical implementation.