Threshold Voltage variation with respect to Gate geometry in Nano-scale MOSFETS

Abstract

The tremendous progress in Metal Oxide Semiconductor (MOS) technology has been a direct consequence of device scaling for past several decades. But as we have entered the nanometer era many problems related to leakage currents and other issues related to variability impacting the yield are of concern. Herein we have investigated how the change in the Fin Architecture and Gate Length of the MOS device impacts the Threshold Voltage.