Optimizing switching performance of MOSFETs in half-bridge topology

Abstract

This paper presents an empirical approach backed by LTspice simulation to optimize switching performance in halfbridge configuration. For a given layout effective value of RC network in gate drive loop, ways to avoid dV/dt induced false turnon of MOSFET and remedial circuit for minimizing parasitic oscillation at switching nodes have been presented. Entire study has been validated using LTspice simulation as it’s not possible to build a hardware board which can cover all the design aspects authors wanted to cover. Idea is to present a systematic approach which a practicing engineer can adopt for optimizing switching of MOSFET in a given PCB layout.