Preprint / Version 1

Power Circuit AI: Designing Power Electronic Circuits for Motor Drives with Generative Artificial Intelligence

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DOI:

https://doi.org/10.31224/6706

Keywords:

Artificial Intelligence, Circuit AI, Electronic Design Automation, Large Language Models, Printed Circuit Boards, Power Electronics, Generative Design

Abstract

The design of power electronic converters is a multiphysics optimization challenge that has traditionally resisted the high levels of automation seen in digital VLSI. While Large Language Models (LLMs) offer a promising interface for capturing high-level design intent, they inherently lack the domain understanding required to generate manufacturing-ready hardware, often resulting in hallucinations and invalid netlists. This paper presents a novel, autonomous multi-agent framework that orchestrates the end-to-end design of power electronic circuits from natural language specifications to clean Printed Circuit Boards (PCBs) without fine-tuning the underlying LLMs. The proposed methodology utilizes a constrained environment to bridge the stochastic gap between generative AI and rigid Electronic Design Automation (EDA) tools. The logical validity of the circuit is ensured by deploying specialized agents for device specification, component selection, SKiDL-based netlist generation, and layout completion. The framework is validated through the autonomous generation of a 400V 3-phase converter for a variable frequency drive. Results demonstrate that while the system achieves 100% logical connectivity and automated routing, transitioning from logical correctness to physics-aware layout optimization and adhering to creepage and clearance requirements remains a critical frontier. The study concludes that pairing LLM agents with deterministic auto routers solves the connectivity problem but requires further integration of physics-based feedback loops to meet the requirements of commutation loop inductance, thermal management, creepage, and clearance requirements. Additionally, it also details the placement limitations within the schematic and flags any components that have not been included.

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Posted

2026-04-02