A Per-Chip Metadata Correction Framework for Neuromorphic Memristor Crossbars: Theoretical Architecture and Viability Analysis

Abstract

Variability in memristor crossbar arrays is conventionally treated as a manufacturing defect to be minimized. This paper reframes it as a deployment problem solvable through per-chip characterisation metadata. We propose a correction framework in which each node's gain coefficient and conductance offset are measured once at fabrication, stored as a compact metadata file, and used to pre-compensate programmed weights at model load time. Under a measurability condition satisfied by published molecular memristor devices, this eliminates per-chip inference error exactly without retraining, hardware-aware training, or inference overhead. Three storage architectures are analysed: DCT compression (2 KB), hybrid tier storage (47 KB), and full per-node storage (312 KB compressed). A heartbeat recalibration protocol maintains correction accuracy over device lifetime. Ten-year energy analysis shows the framework is computationally viable across embedded, laptop, and server deployment contexts. The approach decouples model development from hardware variability, enabling any pre-trained model to be deployed on characterised crossbar hardware without modification.