From Natural Language to a 1.55 GHz Verified GDS on ASAP7 Using Open-Source EDA

Abstract

We carry an RV32I processor end-to-end — RTL generation, verification, and physical design — using an LLM agent on a single workstation, on a consumer subscription with public model access. Four runs are reported. A single-cycle RV32I and a 5-stage forwarding pipeline are taken to DRC-clean GDSII on SkyWater 130 nm at 100 MHz. The 5-stage RTL is then retargeted to ASAP7, closing first-try at 676 ps (1.50 GHz); a tighter SDC sweep with cell sizing alone reaches post-route fmax of 1.55 GHz. All four runs preserve a three-layer verification chain (ISA-grounded golden-trace anchor on the single-cycle reference, pipelined commit-trace alignment for downstream designs, and gate-level simulation on each post-route netlist), passing 40/40 standardized riscv-tests at every layer. Total cost: $9.80 in API-equivalent token usage on a Claude Max 20× $200/month subscription, in 2 h 34 min of wall-clock time across the four runs. Concurrent work reaches a comparable closure target on cloud infrastructure with undisclosed frontier models. We show the same is reachable with public Sonnet through the standard Claude Code CLI, lowering the access barrier for community design-space exploration.