A high-isolation wideband channelizer for MKID readouts: a custom HLS implementation on RFSoC

Abstract

We present a high-performance channelizer for Microwave Kinetic Inductance Detectors (MKIDs), designed to mitigate spectral leakage and scalloping loss through a 50% overlapping polyphase filter bank (PFB). The design is implemented on a Xilinx Zynq UltraScale+ RFSoC ZCU111 using a custom design — primarily in Vitis High-Level Synthesis (HLS), with the time-critical output serializer and glue logic in VHDL — that processes a 4.096 GSPS input stream with a per-branch super-sample rate (SSR) of 16. Rather than relying on aggressive 512 MHz clocking and vendor IP cores, our split-path architecture computes the delayed and non-delayed polyphase branches concurrently, so that the bulk of the channelizer operates at a robust 256 MHz while a single 512 MHz subdomain is confined to the BRAM-to-FFT section. This architectural parallelism enables a deep 16-tap prototype filter that doubles the filter depth of comparable high-speed systems and substantially improves channel isolation. We report the complete internal architecture of the reordering engine that implements the overlap, including two implementation hazards not documented in prior art: a pipeline-stage skew affecting state toggles in HLS, and the state-preservation requirements of a restartable design. The 2/1 overlapped channel response is validated in simulation — recovering the ~3.9 dB scalloping loss of a critically sampled channelizer to below 0.1 dB across the full 2 MHz channel — and characterized systematically with a 100-tone batch frequency sweep, while the parent readout system has been operated cryogenically with an MKID array in an adiabatic demagnetization refrigerator (ADR), identifying individual resonators in total darkness. The result is a resource-efficient, high-isolation benchmark for wideband frequency-division-multiplexed readouts.