SRAM for IoT Applications in 0.6um CMOS
DOI:
https://doi.org/10.31224/osf.io/ydu5jKeywords:
CMOS, low-power, SPI, SRAMAbstract
This article presents the detailed design and implementation of a Static Random-Access Memory (SRAM) in CMOS technology. The data access (read/write) is done through Serial Peripheral Interface (SPI), an industry-standard serial protocol. This SRAM is specifically suitable for Internet-of-Things (IoT) applications with slow access rates and low power consumption. For the purpose of demonstration, a 32-byte SRAM was designed and fabricated in 0.6um CMOS technology and successfully tested for its full functionality after fabrication.Downloads
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