Variation-Aware Thermal Design for Advanced Packaging

A Systematic Review

Abstract

Thermal design of flip-chip, 2.5D and 3D packages uses nominal values of features—bond line thickness, voids, coverage, warpage, die thickness, bonded-interface conductance—that are manufactured outcomes with unit-to-unit distributions. This systematic review, conducted to a protocol written before the search and reported following PRISMA 2020, asks what the peer-reviewed literature reports about the magnitude and distribution of such variation, its thermal effect, the metrology that resolves it, and the statistical and specification practice connecting the three. From 2,253 records screened, 388 studies were included (210 on flip-chip, 2.5D and 3D packages; 178 on power-module and LED die attach as an adjacent comparator); the 142 studies carrying quantitative data were extracted, 136 from full text. Normalised sensitivities from 41 studies show that distributed voids raise thermal resistance by 0.5–1.2% per percentage point of area, whereas contiguous or largest voids raise it by 1.5–9% per point along exponential relations with thresholds of 5–40%; bond line raises resistance by 1–5% per micrometre depending on TIM conductivity; and 36–61 µm of warpage produces corner-to-centre temperature-rise ratios of 1.5–2 when the TIM cannot follow the die. Geometric metrology resolves voids, bond lines and warpage to micrometres, but the gauge repeatability of the inspection metrics behind specifications is reported once, and buried bond interfaces cannot yet be measured non-destructively. Only 72 studies apply a statistical treatment or state a specification, and only five derive a permitted variation from a thermal requirement. A gap map identifies the cells without quantitative evidence and proposes five studies to fill them.