Datapath Width Design Space of 32-Bit RISC-V Processors for 2D Semiconductor Logic

Abstract

The first 32-bit RISC-V processor on a two-dimensional semiconductor, a 5,931-transistor MoS₂ chip, is bit-serial to fit a device-count-limited process. This work determines where the optimal datapath width departs from bit-serial execution. A digit-serial RV32I core of 1 to 32 bits is synthesized onto a model of that process, with every mapping and pipelining step formally proved. Serialization saves only about 2.5× in transistors, not 32×, because control and state do not scale with width. At the fabricated 1 kHz clock a 32-bit core thus delivers 13.5× the throughput at 5.2-5.5× lower energy per instruction. The energy ordering reverses when the throughput is fixed and the core cannot be power-gated. At the 2025 device parameters only yield selects bit-serial execution, above about 250 defects per million transistors if the 17-stage depth rule of the process is a delay budget, or 75 if it is a hard constraint. Mapper quality moves these values by up to 2.3×. Under the Poisson statistics every design yields below 1% at the published defect density, and a 10% die yield requires a 3.6-5.4× lower density, less with defect clustering. With an on-die register file, serialization saves only 11-13% of the transistors, and bit-serial execution is never the widest feasible design. Closed-form boundaries locate other technologies on this width map.