Design and ASIC Implementation of an Edge-AI SoC Subsystem for Detecting Driver Unresponsiveness and Requesting a Minimum Risk Manoeuvre

Abstract

Driver drowsiness and loss of responsiveness are major causes of road accidents, and a warning buzzer alone cannot protect a vehicle whose driver has stopped responding. This paper presents a digital hardware subsystem for Advanced Driver Assistance Systems (ADAS) that takes precomputed class scores (logits) from an upstream Convolutional Neural Network (CNN), judges their reliability, cross-checks them with an independent fatigue indicator, and escalates from a warning to a Minimum Risk Manoeuvre (MRM) request if the driver does not respond. The design contains a CNN confidence unit, a PERCLOS-inspired fatigue unit using a 32-frame sliding window, a safety arbiter and a risk-adaptive finite state machine (FSM) whose response timeout shortens as obstacle and lane-drift risk rises. The Verilog RTL was verified with a 12-scenario testbench in Synopsys VCS and Verdi. Synthesis with Synopsys Design Compiler on the SAED32 library at a 4 ns clock (250 MHz) gave 582 cells, a total cell area of 1726.40 units, 195.69 µW dynamic power and a setup slack of 0.00 ns. A Synopsys IC Compiler II analysis reported 667 cells and 79.38% core utilization. These are pre-layout and placement-stage estimates, and their limitations are stated explicitly.