Experimental Verification of a ±10% Accurate 1‒Dimensional Output Resistance Model for Long Channel Silicon and SiC MOSFETs in Saturation Suitable for Hand Analysis in CMOS IC’s

Abstract

Accurate (±5%) quantitative predictions for the output resistance of MOSFETs operating in their saturation region have long been associated with 2-dimensional (2D) modeling of electric fields near the drain junction. The complexities of such analytical and numerical models tend not only to hinder intuitive appreciation of the dominant effects determining the behavior of the output resistance, but to render them unsuitable for hand analysis, and even for efficient computer-aided design, as well. On the other hand, extant simplified 1-dimensional (1D) models approximating channel shortening by the length of the drain’s depletion region, (a) typically underestimate the output resistance by 50%, (b) fail to account for non-negligible dynamic range degradation, and (c) predict substrate voltage effects qualitatively opposite to observations. These shortcomings are suggestive of underlying conceptual wants.

We elaborate a 1D model of the pinchoff region whose extent  is determined by  (i) an “internal” saturation voltage V_DSAT corresponding to the limit of laminar flow, the objective criterion which obtains as the surface potential transitions from strong to weak inversion and, in view of current continuity, (ii) the inversion charge Q_i injected into the pinchoff region. This concept, underpinned by physical considerations and guided by observations, yields a continuous drain-source conductance through the triode, transition, and pinchoff regions. We develop a simple expression for the saturation region’s incremental conductance whose dominant underlying effects conforming to the EKV model are explicit, and which is suitable for hand analysis and design of well-tempered contemporary circuits down to the limit of planar CMOS (about 20nm). Its accuracy, which is close to modern PSP-based models’, is within experimental and typical process parameter uncertainty (±10%) for silicon and silicon carbide MOSFETs, to whose characteristics we compare it critically.